Threshold voltage determination for calibrating voltage bins of a memory device

ABSTRACT

A processing device of a memory sub-system is configured to identify a plurality of blocks assigned to a first voltage bin of a plurality of voltage bins of a memory device; identify a subset of the plurality of blocks having a time after program (TAP) within a predetermined threshold period of time from a second TAP associated with a transition boundary between the first voltage bin and a subsequent voltage bin of the plurality of voltage bins; determine a threshold voltage offset associated with the subset of blocks; and associate the threshold voltage offset with the subsequent voltage bin.

TECHNICAL FIELD

Embodiments of the disclosure are generally related to memory sub-systems, and more specifically, are related to threshold voltage determination for calibrating voltage bins of a memory device.

BACKGROUND

A memory sub-system can include one or more memory devices that store data. The memory devices can be, for example, non-volatile memory devices and volatile memory devices. In general, a host system can utilize a memory sub-system to store data at the memory devices and to retrieve data from the memory devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The present disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of some embodiments of the disclosure.

FIG. 1 illustrates an example computing system that includes a memory sub-system in accordance with some embodiments of the present disclosure.

FIG. 2 schematically illustrates example metadata maintained by the memory sub-system controller for associating blocks with voltage bins, in accordance with embodiments of the present disclosure.

FIG. 3 illustrates an example method of calibrating voltage bins of a memory device based on threshold voltage offset of blocks approaching a transition boundary between voltage bins, in accordance with one or more aspects of the present disclosure.

FIG. 4 illustrates an example method of calibrating a voltage bin of a memory device by adjusting a threshold voltage offset of the voltage bin to be within a range of threshold voltage offsets, in accordance with one or more aspects of the present disclosure.

FIG. 5 is a flow diagram of an example method of threshold voltage determination for calibrating voltage bins of a memory device, in accordance with some embodiments of the present disclosure.

FIG. 6 is a flow diagram of an example method of calibrating a voltage bin of a memory device by adjusting a threshold voltage offset of the voltage bin based on a voltage threshold, in accordance with one or more aspects of the present disclosure.

FIG. 7 illustrates an example machine of a computer system within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed.

DETAILED DESCRIPTION

Embodiments of the present disclosure are directed to threshold voltage determination for calibrating voltage bins of a memory device. A memory sub-system can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of storage devices and memory modules are described below in conjunction with FIG. 1 . In general, a host system can utilize a memory sub-system that includes one or more components, such as memory devices that store data. The host system can provide data to be stored at the memory sub-system and can request data to be retrieved from the memory sub-system.

A memory sub-system can utilize one or more memory devices, including any combination of the different types of non-volatile memory devices and/or volatile memory devices, to store the data provided by the host system. In some embodiments, non-volatile memory devices can be provided by negative-and (NAND) type flash memory devices. Other examples of non-volatile memory devices are described below in conjunction with FIG. 1 . A non-volatile memory device is a package of one or more dice. Each die can consist of one or more planes. Planes can be grouped into logic units (LUN). For some types of non-volatile memory devices (e.g., NAND devices), each plane consists of a set of physical blocks. A “block” herein shall refer to a set of contiguous or non-contiguous memory pages. An example of “block” is “erasable block,” which is the minimal erasable unit of memory, while “page” is a minimal writable unit of memory. Each page includes of a set of memory cells. A memory cell is an electronic circuit that stores information.

Data operations can be performed by the memory sub-system. The data operations can be host-initiated operations. For example, the host system can initiate a data operation (e.g., write, read, erase, etc.) on a memory sub-system. The host system can send access requests (e.g., write command, read command) to the memory sub-system, such as to store data on a memory device at the memory sub-system and to read data from the memory device on the memory sub-system. The data to be read or written, as specified by a host request, is hereinafter referred to as “host data”. A host request can include logical address information (e.g., logical block address (LBA), namespace) for the host data, which is the location the host system associates with the host data. The logical address information (e.g., LBA, namespace) can be part of metadata for the host data. Metadata can also include error handling data (e.g., error correction code (ECC) parity code), data version (e.g. used to distinguish age of data written), valid bitmap (which LBAs or logical transfer units contain valid data), etc.

A memory device includes multiple memory cells, each of which can store, depending on the memory cell type, one or more bits of information. A memory cell can be programmed (written to) by applying a certain voltage to the memory cell, which results in an electric charge being held by the memory cell, thus allowing modulation of the voltage distributions produced by the memory cell. Moreover, precisely controlling the amount of the electric charge stored by the memory cell allows the establishment of multiple threshold voltage levels corresponding to different logical levels, thus effectively allowing a single memory cell to store multiple bits of information: a memory cell operated with 2 n different threshold voltage levels is capable of storing n bits of information. Thus, the read operation can be performed by comparing the measured voltage exhibited by the memory cell to one or more reference read voltage levels in order to distinguish between two logical levels for single-level cells and between multiple logical levels for multi-level cells.

Due to the phenomenon known as slow charge loss, the threshold voltage of a memory cell changes in time as the electric charge of the cell is degrading, which is referred to as “temporal voltage shift” (since the degrading electric charge causes the voltage distributions to shift along the voltage axis towards lower voltage levels). The threshold voltage changes rapidly at first (immediately after the memory cell was programmed), and then slows down in an approximately logarithmic linear fashion with respect to the time elapsed since the cell programming event. Accordingly, failure to mitigate the temporal voltage shift caused by the slow charge loss can result in the increased bit error rate in read operations.

However, various common implementations either fail to adequately address the temporal voltage shift or employ inefficient strategies resulting in high bit error rates and/or exhibiting other shortcomings. Embodiments of the present disclosure address the above-noted and other deficiencies by implementing a memory sub-system that employs a set of read threshold voltage bins (herein after voltage bins) and assigning each block stored at the memory devices of the memory sub-system voltage one of the voltage bins, based on a time after program of each block and/or a threshold voltage offset that results in efficient read operations of the blocks. Efficient read operation refers to a read operation with low error recovery, thus resulting in low latency. As an example, when a given read operation fails due to high error rate, a subsequent read operation may go through the error handling/error recovery steps to correct the errors. This error recovery process takes time and hence increases latency of returning data to the host. Accordingly, efficient read operation corresponds to low bit error rate which can be achieved by using the appropriate read threshold voltage by accounting for SCL. A voltage bin represents a set of read level threshold voltages that can be used to perform read operation at a given block, such that each read level threshold voltage corresponds to a valley, where each valley is a distance between two adjacent data states of the block to be read. For example, for TLC blocks storing 3 bits, there can be 8 data states (e.g., levels, which can referenced herein as read levels) and 7 valleys. Hence each voltage bin for TLC blocks has 7 offsets one for each valley. In some implementations, reads can be associated with pages and each page type corresponds to certain valleys. For the page reads, appropriate offsets are read from the bin that is assigned to the block containing the page. The one or more valleys of each page type are determined by the code used to map data states (levels) to bits such as the Gray code. Gray code refers to a binary numeral system were two successive valleys differ in only one bit (e.g., binary digit). On TLC blocks, some parts of the block can be multi-level cell (MLC) storing 2 bits per memory cell (resulting in 4 data states), or single level cell (SLC) storing 1 bit per memory cell. For MLC and SLC parts, there can be 3 and 1 offset respectively. The associations of blocks with dies and with voltage bins can be stored in respective metadata tables maintained by the memory sub-system controller.

As explained above, the assignment of blocks of the memory device to voltage bins can reduce the impact of temporal voltage shift caused by the slow charge loss on the efficiency of the read operations of blocks of the memory device. However, slow charge loss, over time, can also impact the efficiency of the read operations for blocks within a single voltage bin. Accordingly, in order to maintain efficient read operations and minimizing bit error rate, a voltage bin calibration process can be performed to adjust threshold voltage offsets associated with each voltage bin. The calibration can involve, for each voltage offset bin, scanning the blocks associated with the voltage bin, e.g., at certain time intervals, determining an updated threshold voltage offset based on the read operations, and updating the threshold voltage offsets of the bin based on the results of the read operations. Scanning each block of the memory device, however, can introduce significant performance penalties to the memory device and can consume considerable bandwidth of the memory device. Thus, embodiments of the present disclosure addresses this limitation by providing techniques to efficiently and proactively perform calibration of blocks approaching a boundary between a given voltage bin and a preceding voltage bin, thus minimizing the performance and bandwidth issues of scanning every block of the memory device.

In accordance with embodiments of the present disclosure, for a given voltage bin, a subset of the blocks that are approaching a transition boundary between the given voltage bin and a subsequent voltage bin (e.g., within a predetermined distance from the transition boundary) can be identified. In one embodiment, each of the voltage bins of the memory device can have a corresponding range of time after program (TAP), such that a programmed block having a TAP value within the range of TAPs of the voltage bin can be assigned to the voltage bin. A transition boundary between the voltage bin and a subsequent voltage bin corresponds to a specific TAP value at one end of the range of TAPs of the voltage bin. When a block that is assigned to a voltage bin reaches a TAP value that is greater than the specific TAP value corresponding to the transition boundary between this voltage bin and the subsequent voltage bin, the block gets re-assigned to the subsequent voltage bin. In certain embodiments, SCL can depend on temperature as well. In this case, TAP can be time after program adjusted with temperature the block experienced. As an example, SCL at 30 C is less than SCL at 90 C. Hence TAP of 30 minutes at 90 C will result in a higher SCL than another SCL after 30 minutes at 30 C. In this case, an adjusted TAP can be computed by taking into account temperature, i.e., a normalized time with respect to a reference temperature such as 30 C. As an example, 30 minutes at 90 C might correspond to a normalized time of approximately 2 hours, for example.

Thus, when the subset of blocks approaching the transition boundary are identified, a threshold voltage offset that is efficient for read operations of the subset of blocks can be determined and then used as the initial threshold voltage offset for the subsequent voltage bin. In one embodiment, the efficient threshold voltage offset of the subset of blocks can be determined by performing read operations of data stored at the subset of blocks and determining the threshold voltage offset that result in the minimum bit error rate of the read operations. Since the subset of blocks approaching the transition boundary will be assigned to the subsequent voltage bin sooner than the other blocks that are assigned to the same voltage bin, the determined threshold voltage offset is assigned as the initial value of the threshold voltage offset of the subsequent voltage bin.

In an embodiment, the subset of blocks approaching the transition boundary for each read level of the set of read levels associated with the voltage bin can be determined, and the threshold voltage offset of the subset of blocks can be assigned as the initial threshold voltage offset of a corresponding read level of the voltage bin. The process of assigning an initial threshold voltage offset can be repeated for each read level of the set of read levels of the subsequent voltage bin.

In certain embodiments, threshold voltage offsets can be assigned to the subsequent voltage bin before assigning blocks storing host data to the subsequent bin. In this case, when threshold voltage offsets are determined and assigned to the subsequent voltage bin, blocks storing host data can be assigned to the subsequent voltage bin. In an embodiment, blocks can be assigned to the subsequent voltage bin based on matching a threshold voltage offset of the blocks, e.g., a threshold voltage offset that results in an efficient read operation of data of the block, with a threshold voltage offset of the subsequent voltage bin. In one embodiment, read operations of blocks assigned to the subsequent voltage bin can be performed using a threshold voltage offset of the subsequent voltage bin.

In some embodiments, as blocks get assigned to a given voltage bin over time, the value of the threshold voltage offset of the voltage bin can continue to be adjusted to enable efficient read operations of data of the assigned blocks. The adjustment of the threshold voltage offset can result in shifting the adjusted threshold voltage offset towards the transition boundary between the given voltage bin and the subsequent voltage bin, thus skewing the threshold voltage offset from its initial value that corresponds to the boundary between the voltage bin and the previous voltage bin. This shift in threshold voltage offset can result in inefficient read operations of blocks that are newly assigned to the voltage bin because the threshold voltage offset may have been shifted significantly, thus may no longer matching an efficient threshold voltage offset for the newly assigned blocks. In order to mitigate the significant shift in the threshold voltage offset of the voltage bin, adjustment of threshold voltage offset during voltage bin calibration can be limited, such that the adjusted threshold voltage offset may not exceed a predetermined voltage threshold. In this case, if the adjusted threshold voltage offset exceeds the predetermined voltage threshold of the voltage bin, the value of the adjusted threshold voltage offset of the voltage bin can be reset to the predetermined voltage threshold of the voltage bin.

Therefore, advantages of the systems and methods implemented in accordance with some embodiments of the present disclosure include, but are not limited to, optimizing the performance of voltage bin calibration process, such that threshold voltage offsets of the voltage bins can be adjusted based on scanning a limited set of blocks while minimizing performance and bandwidth overhead on the memory sub-system. Because a memory sub system can determine an initial threshold voltage offset of a voltage bin based on scanning a set of blocks that are close to transitioning to the voltage bin, a the initial threshold voltage offset can be deemed efficient for performing read operations of blocks assigned to the voltage bin. Additionally, because only the set of blocks approaching the transition boundary are scanned, the performance penalty of the scan process during voltage bin calibration is significantly reduced. Further, by limiting the shifting of the threshold voltage offsets of a given voltage bin over time to a certain maximum threshold, the possibility of significantly shifting the threshold voltage offset for the given voltage bin, causing inefficient read operations of blocks newly assigned to the bin, is minimized.

FIG. 1 illustrates an example computing system 100 that includes a memory sub-system 110 in accordance with some embodiments of the present disclosure. The memory sub-system 110 can include media, such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of such.

A memory sub-system 110 can be a storage device, a memory module, or a hybrid of a storage device and memory module. Examples of a storage device include a solid-state drive (SSD), a flash drive, a universal serial bus (USB) flash drive, an embedded Multi-Media Controller (eMMC) drive, a Universal Flash Storage (UFS) drive, a secure digital (SD) card, and a hard disk drive (HDD). Examples of memory modules include a dual in-line memory module (DIMM), a small outline DIMM (SO-DIMM), and various types of non-volatile dual in-line memory module (NVDIMM).

The computing system 100 can be a computing device such as a desktop computer, laptop computer, network server, mobile device, a vehicle (e.g., airplane, drone, train, automobile, or other conveyance), Internet of Things (IoT) enabled device, embedded computer (e.g., one included in a vehicle, industrial equipment, or a networked commercial device), or such computing device that includes memory and a processing device (e.g., a processor).

The computing system 100 can include a host system 120 that is coupled to one or more memory sub-systems 110. In some embodiments, the host system 120 is coupled to different types of memory sub-systems 110. FIG. 1 illustrates one example of a host system 120 coupled to one memory sub-system 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect communicative connection or direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical, optical, magnetic, etc.

The host system 120 can include a processor chipset and a software stack executed by the processor chipset. The processor chipset can include one or more cores, one or more caches, a memory controller (e.g., NVDIMM controller), and a storage protocol controller (e.g., PCIe controller, SATA controller). The host system 120 uses the memory sub-system 110, for example, to write data to the memory sub-system 110 and read data from the memory sub-system 110.

The host system 120 can be coupled to the memory sub-system 110 via a physical host interface. Examples of a physical host interface include, but are not limited to, a serial advanced technology attachment (SATA) interface, a peripheral component interconnect express (PCIe) interface, universal serial bus (USB) interface, Fibre Channel, Serial Attached SCSI (SAS), a double data rate (DDR) memory bus, Small Computer System Interface (SCSI), a dual in-line memory module (DIMM) interface (e.g., DIMM socket interface that supports Double Data Rate (DDR)), Open NAND Flash Interface (ONFI), Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), etc. The physical host interface can be used to transmit data between the host system 120 and the memory sub-system 110. The host system 120 can further utilize an NVM Express (NVMe) interface to access components (e.g., memory devices 130) when the memory sub-system 110 is coupled with the host system 120 by the PCIe interface. The physical host interface can provide an interface for passing control, address, data, and other signals between the memory sub-system 110 and the host system 120. FIG. 1 illustrates a memory sub-system 110 as an example. In general, the host system 120 can access multiple memory sub-systems via a same communication connection, multiple separate communication connections, and/or a combination of communication connections.

The memory devices 130,140 can include any combination of the different types of non-volatile memory devices and/or volatile memory devices. The volatile memory devices (e.g., memory device 140) can be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

Some examples of non-volatile memory devices (e.g., memory device 130) include negative-and (NAND) type flash memory and write-in-place memory, such as a three-dimensional cross-point (“3D cross-point”) memory device, which is a cross-point array of non-volatile memory cells. A cross-point array of non-volatile memory can perform bit storage based on a change of bulk resistance, in conjunction with a stackable cross-gridded data access array. Additionally, in contrast to many flash-based memories, cross-point non-volatile memory can perform a write in-place operation, where a non-volatile memory cell can be programmed without the non-volatile memory cell being previously erased. NAND type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell. Other types of memory cells, such as multi-level cells (MLCs), triple level cells (TLCs), and quad-level cells (QLCs), can store multiple bits per cell. In some embodiments, each of the memory devices 130 can include one or more arrays of memory cells such as SLCs, MLCs, TLCs, QLCs, or any combination of such. In some embodiments, a particular memory device can include an SLC portion, and an MLC portion, a TLC portion, or a QLC portion of memory cells. The memory cells of the memory devices 130 can be grouped as pages that can refer to a logical unit of the memory device used to store data. With some types of memory (e.g., NAND), pages can be grouped to form blocks.

Although non-volatile memory devices such as 3D cross-point array of non-volatile memory cells and NAND type memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 can be based on any other type of non-volatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selecting memory, other chalcogenide based memories, ferroelectric transistor random-access memory (FeTRAM), ferroelectric random access memory (FeRAM), magneto random access memory (MRAM), Spin Transfer Torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide based RRAM (OxRAM), negative-or (NOR) flash memory, and electrically erasable programmable read-only memory (EEPROM).

A memory sub-system controller 115 (or controller 115 for simplicity) can communicate with the memory devices 130 to perform operations such as reading data, writing data, or erasing data at the memory devices 130 and other such operations. The memory sub-system controller 115 can include hardware such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The hardware can include digital circuitry with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory sub-system controller 115 can be a microcontroller, special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

The memory sub-system controller 115 can include a processor 117 (e.g., processing device) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory sub-system controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines that control operation of the memory sub-system 110, including handling communications between the memory sub-system 110 and the host system 120.

In some embodiments, the local memory 119 can include memory registers storing memory pointers, fetched data, etc. The local memory 119 can also include read-only memory (ROM) for storing micro-code. While the example memory sub-system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, a memory sub-system 110 does not include a controller 115, and can instead rely upon external control (e.g., provided by an external host, or by a processor or controller separate from the memory sub-system).

In general, the memory sub-system controller 115 can receive commands or operations from the host system 120 and can convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 130. The memory sub-system controller 115 can be responsible for other operations such as wear leveling operations, garbage collection operations, error detection and error-correcting code (ECC) operations, encryption operations, caching operations, and address translations between a logical address (e.g., logical block address (LBA), namespace) and a physical address (e.g., physical block address) that are associated with the memory devices 130. The memory sub-system controller 115 can further include host interface circuitry to communicate with the host system 120 via the physical host interface. The host interface circuitry can convert the commands received from the host system into command instructions to access the memory devices 130 as well as convert responses associated with the memory devices 130 into information for the host system 120.

In some implementations, memory sub-system 110 can use a striping scheme, according to which every the data payload (e.g., user data) utilizes multiple dies of the memory devices 130 (e.g., NAND type flash memory devices), such that the payload is distributed through a subset of dies, while the remaining one or more dies are used to store the error correction information (e.g., parity bits). Accordingly, a set of blocks distributed across a set of dies of a memory device using a striping scheme is referred herein to as a “superblock.”

The memory sub-system 110 can also include additional circuitry or components that are not illustrated. In some embodiments, the memory sub-system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., a row decoder and a column decoder) that can receive an address from the controller 115 and decode the address to access the memory devices 130.

In some embodiments, the memory devices 130 include local media controllers 135 that operate in conjunction with memory sub-system controller 115 to execute operations on one or more memory cells of the memory devices 130. An external controller (e.g., memory sub-system controller 115) can externally manage the memory device 130 (e.g., perform media management operations on the memory device 130). In some embodiments, a memory device 130 is a managed memory device, which is a raw memory device combined with a local controller (e.g., local controller 135) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device.

The memory sub-system 110 includes a voltage bin calibration component 113, which can be used to implement techniques for calibrating voltage bins of a memory device 130-140 by adjusting threshold voltage offsets of the voltage bins, in accordance with embodiments of the present disclosure. In one implementation, calibrating a voltage bin may refer to a process of updating one or more threshold voltage offset assigned to the voltage bin based on parameters associated with blocks assigned to the voltage bin including a time after program (TAP) of the blocks, temperature of memory device 130-140 storing the blocks, and/or other parameters. As an example, a voltage bin may be initially calibrated to have a certain threshold voltage offset for a certain read level, which can be used to perform read operations of blocks corresponding to the certain read level. After a period of time, and due to slow charge loss for example, the blocks assigned to the voltage bin can require a different threshold voltage offset for efficient read operations, and thus the voltage bin can be calibrated by adjusting the one or more threshold voltage offsets of the voltage bin to provide efficient read operations of the blocks of the voltage bin. Additionally, voltage bin calibration can be performed to adjust threshold voltage offsets of voltage bins based on die to die variations of memory device 130-140. As an example, an efficient read level voltage threshold for blocks of a given die may be different than an efficient real level voltage offset of another die of the same memory device, due to location of the die, physical characteristics of the die, etc. Accordingly, voltage bin calibration can adjust an initial threshold voltage offset of a read level corresponding to a certain die to reach an efficient threshold voltage offset of the certain die.

Voltage bin calibration can be performed during a pre-characterization process of memory device 130-140, e.g., before assigning blocks storing host data to voltage bins, and/or during a regular use of memory device 130-140, for example in the field of use while storing host data. When used during a pre-characterization process of a memory device, voltage bin calibration can refer to a process of assigning initial threshold voltage offsets to voltage bins of the memory device. In an implementation, voltage bin calibration component 113 can identify a set of blocks assigned to a given voltage bin of the voltage bins of a memory device 130-140, and from the identified blocks can determine a subset of the blocks that are approaching a transition boundary between the voltage bin and a subsequent voltage bin. As an example, voltage bin calibration component 113 can identify the subset of blocks that have a TAP within a predetermined distance from the TAP at the transition boundary. In one implementation, each of the voltage bins of memory device 130-140 has a corresponding range of time after program (TAP) and a transition boundary between a voltage bin and a subsequent voltage bin corresponds to a specific TAP value. In this case, when a block assigned to a given voltage bin reaches a TAP value that is greater than the specific TAP value corresponding to the transition boundary between the given voltage bin and a subsequent voltage bin, the block is assigned to the subsequent voltage bin.

When the subset of blocks approaching the transition boundary are determined, voltage bin calibration component 113 can determine that, since the subset of blocks approaching the transition boundary will be assigned to the subsequent voltage bin sooner than the other blocks that are assigned to the voltage bin, a threshold voltage offset that is efficient for read operations of the subset of blocks can be used as an initial threshold voltage offset for the subsequent voltage bin. In one implementations, an efficient threshold voltage offset of the subset of blocks can be determined by performing read operations of data stored at the subset of blocks and determining a threshold voltage offset that result in a minimum bit error rate of the read operations. Voltage bin calibration component 113 can then assign the efficient threshold voltage offset as the initial value of the threshold voltage offset of the subsequent voltage bin. In an implementation, voltage bin calibration component 113 can determine the subset of blocks approaching the transition boundary for each read level of the set of read levels associated with the voltage bin, and assign the threshold voltage offset of the subset of blocks as the initial threshold voltage offset of a corresponding read level of the voltage bin. Voltage bin calibration component 113 can then repeat the process of assigning an initial threshold voltage offset for each read level of the set of read levels of the subsequent voltage bin.

In certain implementations, when threshold voltage offsets have been assigned to the subsequent voltage bin, voltage bin calibration component 113 can assign blocks storing host data to the subsequent voltage bin. In an implementation, voltage bin calibration component 113 can assign blocks to the subsequent voltage bin based on matching a threshold voltage offset of the blocks. As an example, a threshold voltage offset that results in an efficient read operation of data of the block can be determined and then the block can be assigned to the subsequent voltage bin if the determined threshold voltage offset of the block matches a threshold voltage offset of the subsequent voltage bin. In one implementation, voltage bin calibration component 113 can also perform read operations of blocks assigned to the subsequent voltage bin using a threshold voltage offset of the voltage bin. As an example, to perform a read operation of a block from a certain read level (e.g., L7), voltage bin calibration component 113 can use a threshold voltage offset of a corresponding read level (e.g., L7) out of the set of read level of the subsequent voltage bin.

In some implementations, as blocks get assigned to a given voltage bin over time, the value of a given threshold voltage offset of the voltage bin can continue to be adjusted to enable efficient read operations of data of the assigned blocks. The adjustment of a given threshold voltage offset can result in a shift of the adjusted threshold voltage offset towards a transition boundary between the voltage bin and a subsequent voltage bin, thus skewing the threshold voltage offset from its initial value that corresponds to the boundary between the voltage bin and a previous voltage bin. This shift in threshold voltage offset can result in inefficient read operations of blocks that are newly assigned to the voltage bin because of the shifted threshold voltage offset may have been shifted significantly, thus may no longer match an efficient threshold voltage offset of the newly assigned blocks. In order to mitigate significant shift in a threshold voltage offset of a voltage bin, voltage bin calibration component 113 can limit the adjustment of threshold voltage offset during voltage bin calibration, such that an adjusted threshold voltage offset may not exceed a predetermined voltage threshold. In this case, if an adjusted threshold voltage offset based on voltage bin calibration exceeds the predetermined voltage threshold of the voltage bin, voltage bin calibration component 113 can set the value of the adjusted threshold voltage offset of the voltage bin to the predetermined voltage threshold of the voltage bin.

FIG. 2 schematically illustrates example metadata maintained by the memory sub-system controller for associating blocks and/or partitions with voltage bins, in accordance with embodiments of the present disclosure. As schematically illustrated by FIG. 2 , the memory sub-system controller can maintain the superblock table 210, the block table 220, and the offset table 230. Each record of the superblock table 210 specifies the block associated with the specified superblock and partition combination. In some implementations, the superblock table records can further include time and temperature values associated with the specified superblock and partition combination.

The block table 220 is indexed by the block number, such that each record of the block table 220 specifies, for the block referenced by the index of the record, a set of voltage bins associated with respective dies of the block. In other words, each record of the block table 220 includes a vector, each element of which specifies the voltage bin associated with the die referenced by the index of the vector element.

Finally, the offset table 230 is indexed by the bin number. Each record of the offset table 230 specifies a set of threshold voltage offsets (e.g., for TLC, MLC, and/or SLC) associated with voltage bin. The metadata tables 210-230 can be stored on one or more memory devices 130 of FIG. 1 . In some implementations, at least part of the metadata tables can be cached in the local memory 119 of the memory sub-system controller 115 of FIG. 1 .

In operation, upon receiving a read command, the memory sub-system controller determines the physical address corresponding to the logical block address (LBA) specified by the read command. Components of the physical address, such as the physical block number and the die identifier, are utilized for performing the metadata table walk: first, the superblock table 210 is used to identify the block family identifier corresponding to the physical block number; then, the block identifier is used as the index to the block table 220 in order to determine the voltage bin associated with the block and the die; finally, the identified voltage bin is used as the index to the offset table 230 in order to determine the threshold voltage offset corresponding to the bin. The memory sub-system controller can then additively apply the identified threshold voltage offset to the base voltage read level in order to perform the requested read operation.

In the illustrative example of FIG. 2 , the superblock table 210 maps partition 0 of the superblock 0 to block 4, which is utilized as the index to the block table 220 in order to determine that die 0 is mapped to voltage bin 3. The latter value is used as the index to the offset table in order to determine the threshold voltage offset values for voltage bin 3.

FIG. 3 illustrates an example method of calibrating voltage bins of a memory device based on threshold voltage offset of blocks approaching a transition boundary between voltage bins, in accordance with one or more aspects of the present disclosure. Method 300 may be performed by processing logic that includes hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processor to perform hardware simulation), or a combination thereof. In some embodiments, the method 300 is performed by voltage bin calibration component 113 of FIG. 1 . In one implementation, graph 310 schematically illustrates a set of voltage bins (bin 0 to bin 3), in accordance with embodiments of the present disclosure for a selected read level. Threshold voltage offset curve 315 illustrates the dependency of the threshold voltage offset, on the y-axis, on the time after program (which can be time normalized with respect to a particular temperature), the period of time elapsed since the block had been programmed, on the x-axis for the selected read level. In one implementation, blocks of the memory device that have been programmed within a specified time window are assigned to a voltage bin that corresponds to the time after program of the blocks. As noted herein above, given that wear-leveling can keep program/erase cycles similar on all blocks, the time elapsed after programming and temperature are the main factors affecting the temporal voltage shift. Using normalized time takes into account the temperature profile and hence temperature information is incorporated into the TAP. Accordingly, all blocks programmed within a specific time window (i.e., normalized time window) are presumed to exhibit similar distributions of threshold voltages in memory cells, and thus can be assigned to the same voltage bin and can utilize the same voltage offsets for read operations.

In one implementation, a newly programmed block can be associated with bin 0. Then, the memory sub-system controller can periodically perform a foreground or background calibration process in order to associate each die of every block with one of the predefined threshold voltage bins (bins 0-3 in the illustrative example of FIG. 3 ), which is in turn associated with the voltage offsets to be applied for read operations. The associations of blocks with voltage bins and dies can be stored in respective metadata tables maintained by the memory sub-system controller, as explained in more details herein with respect to FIG. 2 . The threshold voltage offset of FIG. 3 are associated with a single valley. The threshold voltage offset value become more negative going down the y-axis, which corresponds to higher SCL. For each voltage bin, a separate threshold voltage offset can be assigned to each valley.

As schematically illustrated by FIG. 3 , graph 310 can be subdivided into multiple voltage bins 320, such that each voltage bin corresponds to a predetermined range of threshold voltage offsets based on a corresponding range of TAP of the voltage bin. While the illustrative example of FIG. 3 defines four voltage bins, in other implementations, various other numbers of voltage bins can be employed (e.g., 10 bins). Based on a periodically performed calibration process, the memory sub-system controller associates each die of every block with a voltage bin, which defines a set of threshold voltage offsets to be applied to the base voltage read level in order to perform read operations of data of the block, as described in more detail herein below.

Graph 325 of FIG. 3 illustrates the process of calibrating voltage bins by assigning a threshold voltage offset to a voltage bin based on a threshold voltage offset of blocks approaching a transition boundary between voltage bins. In an implementation, a processing logic executing method 300 can determine a time after program (TAP) 330 corresponding to a transition boundary between bin 1 and bin 2. In an implementation, TAP 330 can be a specific value of time elapsed since programming a block. In other implementations, TAP 330 can be a range of values, such that a block having a TAP value that is within the TAP 330 range can be transitioned from voltage bin 1 to voltage bin 2.

In certain implementations, the processing logic can determine a set of blocks assigned to voltage bin 1 that are approaching boundary TAP 330 between voltage bin 1 and voltage bin 2. As an example, the processing logic can determine the set of blocks having a TAP value that is within a predetermined distance from TAP 330. When the set of blocks approaching the transition boundary corresponding to TAP 330 are determined, the processing logic can determine a threshold voltage offset that is efficient for read operations of the determined set of blocks, to be used as an initial threshold voltage offset for the selected read level of voltage bin 2. In an implementation, a set of efficient threshold voltage offsets (one for each valley) of the set of blocks can be determined by performing read operations of data stored at the set of blocks and determining a set of threshold voltage offsets that result in a minimum bit error rate of the read operations. When the set of threshold voltage offsets of the set of blocks is determined, the processing logic can assign the determined threshold voltage offset set as an initial value of the threshold voltage offsets of the selected read level of voltage bin 2. In an implementation, the processing logic can then assign blocks to voltage bin 2 and can utilize the initial value of the threshold voltage offsets to perform read operations of the newly assigned blocks that are associated with the selected read level. For each voltage bin, the set of read offsets includes one offset per valley, such as 7 offsets for TLC wordlines, for example. Page reads correspond to different valleys and as such can use corresponding read offsets. Read operations used to determine the set of read offsets can use different page types to cover all valleys.

Similarly, the processing logic can determine a TAP 340 corresponding to a transition boundary between voltage bin 2 and voltage bin 3. In an implementation, TAP 340 can be a specific value of time elapsed since programming a block. In other implementations, TAP 340 can be a range of values, such that a block having a TAP value that is within the TAP 340 range can be transitioned from voltage bin 2 to voltage bin 3. In certain implementations, the processing logic can determine a set of blocks assigned to voltage bin 2 that are approaching boundary TAP 340 between voltage bin 2 and voltage bin 3. As an example, the processing logic can determine the set of blocks having a TAP value that is within a predetermined distance from TAP 340. When the set of blocks approaching the transition boundary corresponding to TAP 340 are determined, the processing logic can determine a set of threshold voltage offsets that are efficient for read operations of the determined set of blocks, to be used as an initial set of threshold voltage offsets for the selected read level of voltage bin 3. When the set of threshold voltage offsets of the set of blocks is determined, the processing logic can assign the determined threshold voltage offset set as an initial value of the threshold voltage offsets of the selected read level of voltage bin 3. In an implementation, the processing logic can then assign blocks to voltage bin 3 and can utilize the initial values of the threshold voltage offsets to perform read operations of the newly assigned blocks that are associated with the selected read level.

FIG. 4 illustrates an example method 400 of calibrating a voltage bin of a memory device by adjusting threshold voltage offsets of the voltage bin to be within a range of threshold voltage offsets, in accordance with one or more aspects of the present disclosure. Method 400 may be performed by processing logic that includes hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions run on a processor to perform hardware simulation), or a combination thereof. In some embodiments, method 400 is performed by voltage bin calibration component 113 of FIG. 1 . In one implementation, graph 410 schematically illustrates a set of voltage bins (bin 0 to bin 3), in accordance with embodiments of the present disclosure for a selected read level. In one implementation, blocks of the memory device that have been programmed within a specified time window are assigned to a voltage bin 0-3 that corresponds to the time after program of the blocks.

As schematically illustrated by FIG. 4 , graph 410 can be subdivided into multiple voltage bins Bin 0-3, such that each voltage bin corresponds to a predetermined range of threshold voltage offsets based on a corresponding range of TAP of the voltage bin for each valley. While the illustrative example of FIG. 4 defines four voltage bins, in other implementations, various other numbers of voltage bins can be employed (e.g., 10 bins). In certain implementations, initial threshold voltage offset values can be assigned to a selected read level of each voltage bin 0-3 and blocks of the memory device can be assigned to one of voltage bins Bin 0-3 based on an efficient threshold voltage offset of the block and/or a TAP of the block.

In certain implementations, the processing logic can perform voltage bin calibration to adjust threshold voltage offsets of voltage bins, for example to accommodate die to die variations of the memory device. On the other hand, due to the non-linearity of threshold voltage offset versus TAP, as seen on graph 410 corresponding to a single valley, an efficient threshold voltage offset is not a linear function of TAP within a voltage bin as well. Accordingly, as bin voltage calibration is performed, based on blocks currently assigned to the voltage bin, there is a tendency that more statistical block samples for the calibration process are selected from larger TAP within a voltage bin, thus causing a calibrated threshold voltage offset to shift towards the higher TAP within a voltage bin. Shifting the threshold voltage offset can result in less efficient read operations of blocks newly assigned to the voltage bin. To mitigate significant shifts in a threshold voltage offset of a voltage bin 0-3 due to calibration, the processing logic can limit the adjustment of a threshold voltage offset during calibration, such that an adjusted threshold voltage offset may not exceed predetermined voltage threshold 415. In this case, if a calibrated threshold voltage offset of Bin 2 exceeds threshold voltage 415, the processing logic can set the value of the calibrated threshold voltage offset of Bin 1 to the predetermined voltage threshold 415. In an implementation, voltage threshold 415 can be approximately halfway within the range of threshold voltage offset of Bin 1, thus providing an improved read efficiency for newly assigned blocks as well as older blocks of Bin 1.

FIG. 5 is a flow diagram of an example method of threshold voltage determination for calibrating voltage bins of a memory device, in accordance with some embodiments of the present disclosure. The method 500 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 500 is performed by the voltage bin calibration component 113 of FIG. 1 . Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations can be performed in a different order, while some operations can be performed in parallel. Additionally, one or more operations can be omitted in some embodiments. Thus, not all illustrated operations are required in every embodiment, and other process flows are possible.

At operation 510, the processing logic identifies a set of blocks assigned to a voltage bin of a set of voltage bins of a memory device. In one implementation, blocks of the memory device are assigned to voltage bins of the memory device based on a time after program (TAP) of each block after the block has been programmed, such that a TAP of the block matches a TAP of the voltage bin, as explained in more details herein above.

At operation 520, the processing logic identifies a subset of the blocks assigned to the voltage bin that have a TAP that is within a predetermined threshold point in time from a TAP threshold at a transition boundary between the voltage bin and a subsequent voltage bin of the voltage bins of the memory device. In one implementation, blocks approaching a transition boundary between a voltage bin and a subsequent voltage bin can be scanned to determine a corresponding efficient threshold voltage offset which can then be used as an initial threshold voltage offset for a subsequent voltage bin, as explained in more details herein.

At operation 530, the processing logic determines a threshold voltage offset associated with the subset of blocks approaching the transition boundary, for example by performing read operations of the subset of blocks and determining a threshold voltage offset that results in efficient read of data stored at the subset of blocks. Subsequently, at operation 540, the processing logic associates the determined threshold voltage offset with the subsequent voltage bin. In an implementation, the processing logic then can start assigning blocks to the subsequent voltage bin and can use the assigned threshold voltage offset to perform read operations of data stored at the blocks assigned to the subsequent voltage bin, as explained in more details herein above. In certain implementations, Operations 530 and 540 can be done in groups of offsets. As an example, if a particular page type corresponds to valleys i & j, then operations 530 and 540 determine the efficient threshold voltage offsets for valleys i & j. The operations are repeated for other page types to determine the efficient threshold voltage offsets for all valleys for the subsequent voltage bin.

FIG. 6 is a flow diagram of an example method of calibrating a voltage bin of a memory device by adjusting a threshold voltage offset of the voltage bin based on a voltage threshold, in accordance with one or more aspects of the present disclosure. The method 600 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuit, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 600 is performed by the voltage bin calibration component 113 of FIG. 1 . Although shown in a particular sequence or order, unless otherwise specified, the order of the operations can be modified. Thus, the illustrated embodiments should be understood only as examples, and the illustrated operations can be performed in a different order, while some operations can be performed in parallel. Additionally, one or more operations can be omitted in some embodiments. Thus, not all illustrated operations are required in every embodiment, and other process flows are possible. As explained with respect to FIG. 5 , the operations defined by FIG. 6 can be done for different page types to determine the efficient threshold voltage offsets for the valleys associated with the voltage bin.

At operation 610, the processing logic identifies a set of blocks assigned to a voltage bin of voltage bins of a memory device. In one implementation, blocks of the memory device are assigned to voltage bins of the memory device based on a threshold voltage offset of each block, such that a threshold voltage offset of the block matches a threshold voltage offset of the voltage bin, as explained in more details herein above.

At operation 620, the processing logic determines a threshold voltage offset associated with the set of blocks associated with the voltage bin. In one implementation, the processing logic can determine a threshold voltage offset that is an average of threshold voltage offsets of the set of blocks of the voltage bin.

At operation 630, the processing logic identifies a threshold voltage offset of the voltage bin and updates the threshold voltage offset of the voltage bin based on the threshold voltage offset associated with the set of blocks. In one implementation, the threshold voltage offset of the voltage bin corresponds to a read level of the voltage bin (e.g., read level 7) and the set of blocks used got updating the threshold voltage offset of the voltage bin are also associated with the same read level, as explained in more details herein.

At operation 640, the processing logic determines whether the updated threshold voltage offset of the voltage bin exceeds a predetermined voltage threshold. In one implementation, the voltage threshold can be approximately halfway within the range of threshold voltage offset of the voltage bin, such that a calibrated threshold voltage offset of the voltage bin does not exceed the halfway threshold of the range of threshold voltage offset of the voltage bin, as explained in more details herein.

At operation 650, responsive to determining that the updated threshold voltage offset exceeds the predetermined voltage threshold, the processing logic further updates the threshold voltage offset of the voltage bin by assigning the value of the predetermined voltage threshold to the threshold voltage offset of the voltage bin.

FIG. 7 illustrates an example machine of a computer system 700 within which a set of instructions, for causing the machine to perform any one or more of the methodologies discussed herein, can be executed. In some embodiments, the computer system 700 can correspond to a host system (e.g., the host system 120 of FIG. 1 ) that includes, is coupled to, or utilizes a memory sub-system (e.g., the memory sub-system 110 of FIG. 1 ) or can be used to perform the operations of a controller (e.g., to execute an operating system to perform operations corresponding to voltage bin calibration component 113 of FIG. 1 ). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, and/or the Internet. The machine can operate in the capacity of a server or a client machine in client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, a switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term “machine” shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The example computer system 700 includes a processing device 702, a main memory 704 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 718, which communicate with each other via a bus 730.

Processing device 702 represents one or more general-purpose processing devices such as a microprocessor, a central processing unit, or the like. More particularly, the processing device can be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets, or processors implementing a combination of instruction sets. Processing device 702 can also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processing device 702 is configured to execute instructions 726 for performing the operations and steps discussed herein. The computer system 700 can further include a network interface device 708 to communicate over the network 720.

The data storage system 718 can include a machine-readable storage medium 724 (also known as a computer-readable medium) on which is stored one or more sets of instructions 726 or software embodying any one or more of the methodologies or functions described herein. The instructions 726 can also reside, completely or at least partially, within the main memory 704 and/or within the processing device 702 during execution thereof by the computer system 700, the main memory 704 and the processing device 702 also constituting machine-readable storage media. The machine-readable storage medium 724, data storage system 718, and/or main memory 704 can correspond to the memory sub-system 110 of FIG. 1 .

In one embodiment, the instructions 726 include instructions to implement functionality corresponding to voltage bin calibration component 113 of FIG. 1 . While the machine-readable storage medium 724 is shown in an example embodiment to be a single medium, the term “machine-readable storage medium” should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term “machine-readable storage medium” shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The term “machine-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed descriptions have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the ways used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure can refer to the action and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present disclosure also relates to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general purpose systems can be used with programs in accordance with the teachings herein, or it can prove convenient to construct a more specialized apparatus to perform the method. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages can be used to implement the teachings of the disclosure as described herein.

The present disclosure can be provided as a computer program product, or software, that can include a machine-readable medium having stored thereon instructions, which can be used to program a computer system (or other electronic devices) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., a computer) readable storage medium such as a read only memory (“ROM”), random access memory (“RAM”), magnetic disk storage media, optical storage media, flash memory components, etc.

In the foregoing specification, embodiments of the disclosure have been described with reference to specific example embodiments thereof. It will be evident that various modifications can be made thereto without departing from the broader spirit and scope of embodiments of the disclosure as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense. 

What is claimed is:
 1. A system comprising: a memory device; and a processing device, operatively coupled to the memory device, to perform operations comprising: identifying a plurality of blocks assigned to a first voltage bin of a plurality of voltage bins of a memory device; identifying a subset of the plurality of blocks having a time after program (TAP) within a predetermined threshold period of time from a second TAP associated with a transition boundary between the first voltage bin and a subsequent voltage bin of the plurality of voltage bins; determining a threshold voltage offset associated with the subset of blocks; and associating the threshold voltage offset with the subsequent voltage bin.
 2. The system of claim 1, wherein the subset of the plurality of blocks is associated with a first read level of a first plurality of read levels of the first voltage bin, and wherein the threshold voltage offset is associated with a second read level of a second plurality of read levels of the subsequent voltage bin.
 3. The system of claim 1, wherein the subset of the plurality of blocks are to be transitioned to the subsequent voltage bin at a first point in time, wherein blocks other than the subset of the plurality of blocks are transitioned to the subsequent voltage bin at a second point in time, and wherein the first point in time precedes the second point in time.
 4. The system of claim 1, wherein determining the threshold voltage offset comprises: performing read operations on data stored at the subset of blocks; and determining the threshold voltage offset based on results of the read operations, wherein the read operations correspond to a plurality of page types, and wherein the threshold voltage offset is one of a plurality of threshold voltage offsets corresponding to valleys of the page types.
 5. The system of claim 1, wherein the processing device is to perform further operations comprising: responsive to associating the threshold voltage offset with the subsequent voltage bin, assigning blocks storing host data to the subsequent voltage bin based on the threshold voltage offset.
 6. The system of claim 1, wherein the processing device is to perform further operations comprising: performing read operations for blocks assigned to the subsequent voltage bin using the threshold voltage offset; updating the threshold voltage offset of the subsequent voltage bin based on results of the read operations; and responsive to determining that the updated threshold voltage offset exceeds a predetermined voltage threshold, assigning a value of the predetermined voltage threshold to the threshold voltage offset associated with the subsequent voltage bin.
 7. The system of claim 1, wherein the TAP of the plurality of blocks corresponds to a normalized time with respect to a reference temperature.
 8. A method comprising: identifying a plurality of blocks assigned to a voltage bin of a plurality of voltage bins of a memory device; performing a set of read operations on data stored at the plurality of blocks; updating a threshold voltage offset associated with the voltage bin based on results of the set of read operations; determining whether the updated threshold voltage offset exceeds a predetermined voltage threshold; and responsive to determining that the updated threshold voltage offset exceeds the predetermined voltage threshold, assigning a value of the predetermined voltage threshold to the threshold voltage offset associated with the voltage bin.
 9. The method of claim 8, wherein the threshold voltage offset is associated with a subset of the plurality of blocks having a same read level of a plurality of read levels of the voltage bin, and wherein the updated threshold voltage offset is associated with a corresponding read level of the plurality of read levels of the voltage bin.
 10. The method of claim 9, wherein determining the threshold voltage offset associated with the plurality of blocks comprises: performing read operations on data stored at the subset of the plurality of blocks; and determining the threshold voltage offset based on results of the read operations.
 11. The method of claim 8 further comprising: responsive to updating the threshold voltage offset, performing read operations for blocks assigned to the voltage bin using the updated threshold voltage offset.
 12. The method of claim 8 further comprising: responsive to updating the threshold voltage offset, assigning blocks of the memory device to the voltage bin based on the updated threshold voltage offset.
 13. The method of claim 8, wherein the updated threshold voltage offset of the voltage bin is determined based on a corresponding threshold voltage offset associated with a set of blocks having a time after program (TAP) within a predetermined threshold point in time from a second TAP associated with a transition boundary between the voltage bin and a preceding voltage bin of the plurality of voltage bins of the memory device.
 14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: identifying a plurality of blocks assigned to a first voltage bin of a plurality of voltage bins of a memory device; determining a subset of the plurality of blocks having a time after program (TAP) within a predetermined threshold point in time from a second TAP associated with a transition boundary between the first voltage bin and a subsequent voltage bin of the plurality of voltage bins; determining a threshold voltage offset associated with the subset of blocks; and associating the threshold voltage offset with the subsequent voltage bin.
 15. The non-transitory computer-readable storage medium of claim 14, wherein the subset of the plurality of blocks is associated with a first read level of a first plurality of read levels of the first voltage bin, and wherein the threshold voltage offset is associated with a second read level of a second plurality of read levels of the subsequent voltage bin.
 16. The non-transitory computer-readable storage medium of claim 14, wherein the subset of the plurality of blocks are to be transitioned to the subsequent voltage bin at a first point in time, wherein blocks other than the subset of the plurality of blocks are transitioned to the subsequent voltage bin at a second point in time, and wherein the first point in time precedes the second point in time.
 17. The non-transitory computer-readable storage medium of claim 14, wherein determining the threshold voltage offset comprises: performing read operations on data stored at the subset of blocks; and determining the threshold voltage offset based on results of the read operations.
 18. The non-transitory computer-readable storage medium of claim 14, wherein the threshold voltage offset is assigned to the subsequent voltage bin before blocks of the memory device are assigned to the subsequent voltage bin.
 19. The non-transitory computer-readable storage medium of claim 14, wherein the processing device is to perform further operations comprising: responsive to associating the threshold voltage offset with the subsequent voltage bin, assigning blocks storing host data to the subsequent voltage bin based on the threshold voltage offset.
 20. The non-transitory computer-readable storage medium of claim 14, wherein the processing device is to perform further operations comprising: performing read operations for blocks assigned to the subsequent voltage bin using the threshold voltage offset; updating the threshold voltage offset of the subsequent voltage bin based on results of the read operations; and responsive to determining that the updated threshold voltage offset exceeds a predetermined voltage threshold, assigning a value of the predetermined voltage threshold to the threshold voltage offset associated with the subsequent voltage bin. 